This invention relates in general to bipolar memory circuits, and more particularly, to a bipolar memory cell biasing technique for setting the power dissipation level of the memory cell array while achieving higher performance.
The use of bipolar technology for memory cells is well known in the art and appreciated for its high speed performance. One such memory cell, commonly known as Wiedmann/Berger cell, provides an excellent trade-off between cell size, power consumption, cell stability and improved alpha immunity as described in an article entitled "Small Size Low-Power Bipolar Memory Cell" by Siegfried K. Wiedmann and Horst H. Berger, published IEEE Journal, Solid State Circuits, vol. SC-6, pages 283-288, October 1971. With the addition of some innovative circuit techniques the memory cell may also provide excellent read/write performance. Briefly, the Wiedmann/Berger memory cell comprises a common-base pair of lateral PNP transistors operating as current source loads for the collector-emitter conduction paths of another pair of cross-coupled NPN bipolar transistors which store a single bit of data. The cross-coupled bipolar transistors are operated in inverse mode. The collectors of the cross-coupled transistor pairs of every memory cell in a row are coupled together forming a word select line.
In the original Wiedmann/Berger memory cell, the bases of the lateral PNP transistors were biased by a reference voltage which establishes the memory cell standby current while simultaneously operating the PNP transistors as active current source loads. However, because of the exponential relationship between the base-emitter junction potential and the associated collector current flowing through the lateral PNP transistors, the memory cells were susceptible to wide variations in standby current flow and associated power consumption. For example, an 18 millivolt variation in the reference potential translates to a factor of two change in the collector current, say from one microamp to two microamps. Consequently, the memory cell array standby current can easily be doubled due to the variation in reference potential.
More recent versions of the Wiedmann/Berger memory cell include an NPN transistor having a collector coupled to the bases of the lateral PNP transistors and an emitter coupled to the word select line. The collector of the NPN transistor is also coupled to the bases of the lateral PNP transistors of the other memory cells in the same row. The base of the NPN transistor is driven by a word select signal which enables an entire row of memory cells. Thus, the bases of the lateral PNP transistors in the memory cell row are biased by the collector current of the word select driver NPN transistor instead of a reference potential thus providing immunity from variations thereof. In addition, a current source is coupled to the word select line of the memory cell row for providing a kicker current to discharge the selected word line. While this improves the variation of current flowing through the memory cell due to the reference potential instability, it creates a similar problem for the lateral PNP transistors in the selected row as the kicker current is distributed as lateral PNP base current from the selected row. This additional base current develops undesirable charges on the large diffusion and junction capacitances of the lateral PNP transistors which must be discharged thereby slowing cycle time and degrading performance.
Hence, what is needed is an improved bipolar memory circuit which limits the effect of the discharge current flowing through the word select driver NPN transistor upon the lateral PNP transistor current source loads.